(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for System On Package (SOP) applications using ceramic as a base packaging medium.
(2) Description of the Prior Art
The art of semiconductor device creation has, since its inception, been characterized by a rapid creation of new technologies and by the development of new and improved methods of using existing processes and materials. The main emphasis during this period of growth has been to achieve improvements in device performance, which in most cases is achieved by reducing the size of device elements to the maximum extent possible. With this reduction in size has come a continuing increase in device density and the creation of more complex devices that provide more complex functions at competitive prices.
The evolutionary process of the semiconductor technology has not been limited to addressing numerous aspects of the creation of semiconductor devices, this process has also had a significant impact on the method in which the semiconductor devices are packaged. Numerous new packaging approaches have been developed over the years by not only creating supporting units or packages that can contain one or more semiconductor devices but by in addition adapting these devices so that they can be readily mounted in a particular package. This has led to many configurations of integrated circuit devices such as Ball Grid Array (BGA), Land Grid Array (LGA) and Pin Grid Array (PGA), Chip Scale Packaging (CSP) and Quad Flat Pack (QFP) devices. A number of approaches in packaging semiconductor devices use plastic packaged modules of the type wherein the contact zones of the chip are connected by wire bonding to lead conductors and wherein the chip is molded in etch resistant resins. Other applications use unpackaged or bare semiconductor die to construct multi chip modules and other electronic devices. Packages that can be used to package IC die can be identified among others as thin quad flat packages (TQFP""s), ball grid arrays (BGA""s), tape automated bonding (TAB), ultra-thin packages, bare chips and chip on board (COB), flip-chip assemblies and multichip modules (MCM""s).
In the field of high density interconnect technology, many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a multi-chip chip module (MCM). To achieve a high wiring and packing density, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. Typically, metal power and ground planes in the substrate are separated by layers of a dielectric such as a polyimide. Embedded in other dielectric layers are metal conductor lines with vias (holes or conductive plugs) providing electrical connections between signal lines or to the metal power and ground planes.
From the above it is clear that a significant effort of the semiconductor industry is aimed at providing the maximum number of functional components while these components are packaged in a minimum amount of space. This leads to the effort of providing complete system functions in one package, whereby the concept of system implies that the function that is provided by the package extends considerably from what is typically considered the function of a semiconductor device. The System On Package (SOP) application addresses not only the packaging of active semiconductor devices but includes the packaging of passive electrical components such as resistors, capacitors and inductors. The invention addresses such a SOP package, using ceramic as a base packaging medium.
U.S. Pat. No. 6,108,212 (Lach et al.) shows a package with passive elements (capacitor and resistors).
U.S. Pat. No. 6,143,401 (Fischer et al.) U.S. Pat. No. 5,854,534 (Beilin et al.) and U.S. Pat. No. 6,015,722 (Banks et al.) show related packages.
A principle objective of the invention is to provide a method that allows for a higher Input/Output (I/O) pin count over a given substrate area by applying a grid area array approach as opposed to a peripheral area approach.
Another objective of the invention is to, for a given component configuration, reduce the required substrate area by using backside I/O ball interconnects, thereby not allocating substrate surface area to individual electrical components.
Yet another objective of the invention is to provide a method of packaging semiconductor devices whereby these devices are packaged face up, thereby providing improved heat dissipation for the device and providing a means for easy interfacing with an additional heat spreader or heat sink.
A sill further objective of the invention is to provide a standard structure for the implementation of System On Package applications, the standard structure can be personalized using thin film processing technology.
In accordance with the objectives of the invention, a new method and structure is provided to create a System On Package (SOP). The process starts with a green sheet that is typically used as the basis for a ceramic substrate. One or more layers of dielectric such as polyimide are deposited over the surface of the ceramic substrate, patterned and etched to created openings in the one or more layers of dielectric that align with conductive plugs that have been provided in the ceramic substrate. Passive components and metal interconnections can be created on the surface of the layers of dielectric using thin film technology. As a final step, a protective layer of dielectric is deposited over the surface of the top layer of dielectric. Active semiconductor devices may be attached to the surface of the SOP, heat sinks can be attached to the semiconductor devices. The SOP may further be mounted on the surface of a Printed Circuit Board or may be connected to a connector of a card or module with metal fingers being connected with points of electrical contact provided in a connector of the card or module.